This invention relates to a method of producing semiconductor devices, particularly, to improvements in the method of forming the electrodes and wiring layers of semiconductor devices.
It is a matter of serious concern in this field to enhance the integration degree of semiconductor elements. However, the construction of conventional semiconductor devices leaves room for further improvements in the integration degree as described in the following with reference to FIGS. 1 to 4. Specifically, each of FIGS. 1 and 3 is a plan view showing the construction of a conventional MOS type field effect transistor. FIG. 2 is a cross sectional view along line II--II of FIG. 1 and FIG. 4 shows the cross section along line IV--IV of FIG. 3.
As shown in FIGS. 1 and 2, a conventional MOS type field effect transistor comprises, for example, a silicon substrate 3 and an insulation film 4, e.g. silicon oxide film, formed on the surface of the substrate 3. Further, a diffusion layer 1 acting as the source or drain region of the transistor is formed in the substrate 3. In general, a contact hole 5 is formed in the insulation film 4 for providing an electrode 2 consisting of, for example, aluminum in direct contact with the diffusion layer 1. Incidentally, reference numeral 6 shown in FIG. 2 denotes a gate oxide film of the transistor. It is seen that a gate electrode 7 consisting of, for example, polycrystalline silicon, hereinafter referred to as "poly-Si," is formed on the gate oxide film 6. Further, a field oxide film 8 is formed as shown in the drawing.
In the conventional MOS type field effect transistor shown in FIGS. 1 and 2, the area required for forming a single contact hole is determined by (a+b+c).times.W, where "a" is the distance between the mutually facing edges of gate electrode 7 and the contact hole 5, "b" is the distance between the mutually facing edges of the contact hole 5 and the field oxide film 8, "c" is the width of the contact hole 5, and "W" is the gate width. In general, the insulation film 4 is formed relatively thick, e.g., about 5000 .ANG. to 1.mu. thick. It follows that the wall of the insulation film 4 defining the contact hole 5 is inclined as shown in FIG. 2, leading to increases in distances "a" and "b" mentioned above. Further, it is difficult to make the contact hole 5 sufficiently small, namely, distance "c" mentioned above is inevitably made large. In other words, the conventional transistor necessitates a large area for forming a contact hole, resulting in that it is difficult to enhance the integration degree of semiconductor elements in the production of an IC, an LSI, etc.
FIGS. 3 and 4 collectively show another kind of conventional MOS type field effect transistor. In this case, a first poly-Si layer consisting of a gate 10 and a wiring layer 11 is covered with an insulation film 12 such as a silicon oxide film. As shown in the drawing, the insulation film 12 is provided with a contact hole 13 and, then, a second poly-Si layer 14 acting as a conductive layer is formed on the insulation film 12 so as to bring the second poly-Si layer 14 into direct contact with the first poly-Si layer, i.e., the gate 10 and the wiring layer 11. Alternatively, the first insulation film covering the first poly-Si layer is covered with a second poly-Si layer and, then, with a second insulation film, followed by providing the first and second insulation films with contact holes. In this case, a metal wiring layer is formed in a manner to fill the contact holes, thereby connecting the first and second poly-Si layers. In such arts, however, the first poly-Si layer should be formed in a manner to provide a sufficient room against deviation in the step of mask-aligning to form the contact hole 13. In addition, it is substantially impossible to provide the contact hole 13 above the gate 10 in view of the required room making up for the mask deviation mentioned above. As a result, it was customary to provide a contact hole above a field oxide film for connecting a conductive layer to the gate 10 as shown in FIG. 4.
To reiterate, the conventional method necessitates a large area for forming a contact hole. In addition, the required area is further enlarged for avoiding the gate-conductive layer connection above the gate.